OMAP3525-HIREL Datasheet, PDF (118/239 Pages) Texas Instruments – OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
4.3.3 DPLLs and DLL Characteristics
Several specifications characterize the seven DPLLs.
Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating
conditions.
NAME
PARAMETER
vdds_dpll_per
vdds_dpll_dll
T_J
Junction temperature
f_input
f_internal
Input reference frequency⁽²⁾
Internal reference frequency
f_output
f_output*2
t_lock
CLKOUT output frequency
CLKOUTx2 output
frequency
Frequency lock time⁽³⁾
p_lock
Phase lock time
t_relock
Relock time – frequency
lock ⁽⁴⁾
p_relock
Relock time – Phase lock⁽⁴⁾
Table 4-14. DPLL Characteristics
MIN
TYP
MAX UNIT
COMMENTS ⁽¹⁾
1.71
1.8
1.89
V At ball level (+5%, +10%)
1.71
1.8
1.89
V
–40
25
107
°C Will not unlock after lock over this range for
slow temperature drifts
0.75
65
MHz FINP
0.75
2.1
MHz FREQSEL3 = 0; FINT = FINP/(N+1)
7.5
21
MHz FREQSEL3 = 1; FINT = FINP/(N+1)
25
900
MHz
50
1800
MHz
71.4
37.1
166.7
46.7
4.8
4.8
19
19
71.4
11.9
95.2
26.7
200
104
466.7
130.7
13.3
13.3
53.3
53.3
200
33.3
266.7
74.7
µs 150 FINT cycles; FREQSEL3 = 0
µs 780 FINT cycles; FREQSEL3 = 1
µs 350 FINT cycles; FREQSEL3 = 0
µs 980 FINT cycles; FREQSEL3 = 1
µs 10 FINT cycles
Lowcurrstby = 0; FREQSEL3 = 0
µs 100 FINT cycles
Lowcurrstby = 0; FREQSEL3 = 1
µs 40 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 0
µs 400 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 1
µs 150 FINT cycles
Lowcurrstby = 0; FREQSEL3 = 0
µs 250 FINT cycles
Lowcurrstby = 0; FREQSEL3 = 1
µs 200 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 0
µs 560 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 1
Table 4-15 and Table 4-16 show the DPLL1 and DPLL2 clock frequency ranges.
Note: The DPLL1 and DPLL2 clock frequency ranges depend on the V_DD1 (vdd_mpu_iva) operating point.
(1) f_reqsel needs to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted
DPLL power state (dynamic).
Lowcurrstdby = 0 then DPLL is in normal mode
Lowcurrstdby = 1 then DPLL is in low-power mode
(2) Input frequencies below 0.75 MHz are possible with performance penalty.
(3) Maximum frequency for nominal conditions. Speed binning possible above fmax.
(4) Relock time assumes typical operating conditions, 4°C maximum temperature drift (see the Functional Specification for more detailed
information).
118 CLOCK SPECIFICATIONS
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