AM1707_1004 Datasheet, PDF (170/198 Pages) Texas Instruments – AM1707 ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
6.28.3 HPI Electrical Data/Timing
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Table 6-99. Timing Requirements for Host-Port Interface Cycles^{(1) (2)}
No.
PARAMETER
MIN
1
t_{su(SELV-HSTBL)}
Setup time, select signals⁽³⁾ valid before UHPI_HSTROBE low
5
2
t_{h(HSTBL-SELV)}
Hold time, select signals⁽³⁾ valid after UHPI_HSTROBE low
2
3 t_w(HSTBL)
Pulse duration, UHPI_HSTROBE active low
15
4 t_w(HSTBH)
Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses
2M
9
t_{su(SELV-HASL)}
Setup time, selects signals valid before UHPI_HAS low
5
10 t_h(HASL-SELV)
Hold time, select signals valid after UHPI_HAS low
2
11 t_{su(HDV-HSTBH)}
Setup time, host data valid before UHPI_HSTROBE high
5
12 t_h(HSTBH-HDV)
Hold time, host data valid after UHPI_HSTROBE high
2
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE
13 t_{h(HRDYL-HSTBH)} should not be inactivated until UHPI_HRDY is active (low); otherwise, HPI
2
writes will not complete properly.
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
16 t_{su(HASL-HSTBL)}
17 t_{h(HSTBL-HASH)}
Setup time, UHPI_HAS low before UHPI_HSTROBE low
Hold time, UHPI_HAS low after UHPI_HSTROBE low
2
ns
2
ns
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(3) Select signals include: HCNTL[1:0], HR/W and HHWIL.
170 Peripheral Information and Electrical Specifications
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