AM1707_1004 Datasheet, PDF (112/198 Pages) Texas Instruments – AM1707 ARM Microprocessor

AM1707
SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010
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Table 6-55. General Timing Requirements for SPI0 Slave Modes⁽¹⁾
No.
PARAMETER
9 t_c(SPC)S
Cycle Time, SPI0_CLK, All Slave Modes
10 t_w(SPCH)S
11 t_w(SPCL)S
Pulse Width High, SPI0_CLK, All Slave Modes
Pulse Width Low, SPI0_CLK, All Slave Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Setup time, transmit data written to SPI
12 t_{su(SOMI_SPC)S} before initial clock edge from master.⁽²⁾
(3)
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Delay, subsequent bits valid on
13 t_{d(SPC_SOMI)S} SPI0_SOMI after transmit edge of
SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
14
t_{oh(SPC_SOMI)S}
Output hold time, SPI0_SOMI valid afte
receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
15
t_{su(SIMO_SPC)S}
Input Setup Time, SPI0_SIMO valid
before receive edge of SPI0_CLK
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
16
t_{ih(SPC_SIMO)S}
Input Hold Time, SPI0_SIMO valid after
receive edge of SPI0_CLK
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
MIN
greater of 2P or
20 ns
18
18
2P
2P
2P
2P
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0.5t_c(SPC)S -3
0
0
0
0
5
5
5
5
MAX
256P
18.5
18.5
18.5
18.5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the CPU.
112 Peripheral Information and Electrical Specifications
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