CC2550_06 Datasheet, PDF (17/55 Pages) Texas Instruments – Single Chip Low Cost Low Power RF Transmitter

CC2550
The PATABLE is an 8-byte table that defines
the PA control settings to use for each of the
eight PA power values (selected by the 3-bit
value FREND0.PA_POWER). The table is
written and read from the lowest setting (0) to
the highest (7), one byte at a time. An index
counter is used to control the access to the
table. This counter is incremented each time a
byte is read or written to the table, and set to
the lowest index when CSn is high. When the
highest value is reached the counter restarts at
0.
The access to the PATABLE is either single
byte or burst access depending on the burst
bit. When using burst access the index counter
will count up; when reaching 7 the counter will
restart at 0. The read/write bit controls whether
the access is a write access (R/W=0) or a read
access (R/W=1).
If one byte is written to the PATABLE and this
value is to be read out then CSn must be set
high before the read access in order to set the
index counter back to zero.
Note that the content of the PATABLE is lost
when entering the SLEEP state.
11 Microcontroller Interface and Pin Configuration
In a typical system, CC2550 will interface to a
microcontroller. This microcontroller must be
able to:
• Program CC2550 into different modes
• Write buffered data
• Read back status information via the 4-wire
SPI-bus configuration interface (SI, SO,
SCLK and CSn)
11.1 Configuration Interface
The microcontroller uses four I/O pins for the
SPI configuration interface (SI, SO, SCLK and
CSn). The SPI is described in 13 on page 13.
11.2 General Control and Status Pins
The CC2550 has one dedicated configurable
pin and one shared pin that can output internal
status information useful for control software.
These pins can be used to generate interrupts
on the MCU. See Section 24 page 30 for more
details of the signals that can be programmed.
The dedicated pin is called GDO0. The shared
pin is the SO pin in the SPI interface. The
default setting for GDO1/SO is 3-state output.
By selecting any other of the programming
options the GDO1/SO pin will become a
generic pin. When CSn is low, the pin will
always function as a normal SO pin.
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX
data input pin while in transmit mode.
The GDO0 pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external ADC,
the temperature can be calculated.
Specifications for the temperature sensor are
found in Section 4.5 on page 7.
With default PTEST register setting (0x7F) the
temperature sensor output is only available
when the frequency synthesizer is enabled
(e.g. the MANCAL, FSTXON and TX states).
It is necessary to write 0xBF to the PTEST
register to use the analog temperature sensor
in the IDLE state. Before leaving the IDLE
state, the PTEST register should be restored to
its default value (0x7F).
PRELIMINARY Data Sheet (Rev.1.2) SWRS039A
Page 17 of 54