CC2543 Datasheet, PDF (17/29 Pages) Texas Instruments – System-on-Chip for 2.4-GHz RF Applications

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CC2543
SWRS107B – APRIL 2012 – REVISED MAY 2012
Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit
overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the
exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflow-
compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and
TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has
its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured
as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling
scheme, and are thus well-suited for high data rates.
The I²C module provides a digital peripheral connection with two pins and supports both master and slave
operation.
The ADC supports 7 bits (30 kHz bandwidth) to 12 bits (4 kHz bandwidth) of resolution. DC and audio
conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or
differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The
ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or
conversion over a sequence of channels.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is mapped into the digital I/O port and can be treated by the MCU as a regular digital input.
Copyright © 2012, Texas Instruments Incorporated
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