CC2543 Datasheet, PDF (15/29 Pages) Texas Instruments – System-on-Chip for 2.4-GHz RF Applications

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CC2543
SWRS107B – APRIL 2012 – REVISED MAY 2012
BLOCK DIAGRAM
A block diagram of the CC2543 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's
Guide (SWRU283) for more details.
RESET_N
XOSC_Q2
XOSC_Q1
RESET
32 MHz
CRYSTAL OSC
WATCHDOG TIMER
CLOCK MUX &
CALIBRATION
DEBUG
INTERFACE
HIGH SPEED 32 kHz
RC-OSC RC-OSC
POWER ON RESET
BROWN OUT
ON-CHIP VOLTAGE
REGULATOR
VDD (2.0 - 3.6 V)
DCOUPL
SLEEP TIMER
POWER MGT. CONTROLLER
P2_2
P2_1
P2_0
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
8051 CPU
CORE
DMA
PDATA
XRAM
IRAM
SFR
UNIFIED
MEMORY
ARBITRATOR
RAM
SRAM
FLASH
FLASH
IRQ
CTRL
ANALOG COMPARATOR
PSEUDO
RANDOM
NUMBER
GENERATOR
DS ADC
AUDIO / DC
AES
ENCRYPTION
&
DECRYPTION
FLASH CTRL
FIFOCTRL
SRAM
RADIO
REGISTERS
ROM
Link Layer Engine
DEMODULATOR
MODULATOR
SDA
SCL
USART 0
I²C
TIMER 1 (16-bit)
TIMER 2
(RADIO TIMER)
TIMER 3 (8-bit)
TIMER 4 (8-bit)
RECEIVE
TRANSMIT
DIGITAL
ANALOG
MIXED
RF_P RF_N
Figure 7. CC2543 Block Diagram
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s) :CC2543
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