OPA354 Datasheet, PDF (16/23 Pages) Texas Instruments – 250MHz, Rail-to-Rail I/O, CMOS OPERATIONAL AMPLIFIERS

OPA354
OPA2354
OPA4354
SBOS233D − MARCH 2002− REVISED FEBRUARY 2005
The PowerPAD package is designed so that the leadframe
die pad (or thermal pad) is exposed on the bottom of the
IC, as shown in Figure 9. This provides an extremely low
thermal resistance (q_JC) path between the die and the
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the
PCB as a heatsink. In addition, plated-through holes (vias)
provide a low thermal resistance heat flow path to the back
side of the PCB.
Leadframe (Copper Alloy)
IC (Silicon)
Die Attach (Epoxy)
Mold Compound (Plastic)
Leadframe Die Pad
Exposed at Base of the Package
(Copper Alloy)
Figure 9. Section View of a PowerPAD Package
www.ti.com
4. It is recommended, but not required, to place a small
number of additional holes under the package and outside
the thermal pad area. These holes provide additional heat
paths between the copper thermal land and the ground
plane. They may be larger because they are not in the area
to be soldered, so wicking is not a problem. This is
illustrated in Figure 10.
5. Connect all holes, including those within the thermal pad
area and outside the pad area, to the internal ground plane
or other internal copper plane for single-supply
applications, and to V− for split-supply applications.
6. When laying out these holes, do not use the typical web
or spoke via connection methodology, as shown in
Figure 11. Web connections have a high thermal
resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes soldering
the vias that have ground plane connections easier.
However, in this application, low thermal resistance is
desired for the most efficient heat transfer. Therefore, the
holes under the PowerPAD package should make their
connection to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
PowerPAD ASSEMBLY PROCESS
1. The PowerPAD must be connected to the device’s most
negative supply voltage, which will be ground in
single-supply applications, and V− in split-supply
applications.
2. Prepare the PCB with a top-side etch pattern, as shown
in Figure 10. The exact land design may vary based on the
specific assembly process requirements. There should be
etch for the leads as well as etch for the thermal land.
Thermal Land
(Copper)
Minimum Size
4.8mm x 3.8mm
(189 mils x 150 mils)
OPTIONAL:
Additional 4 vias outside
of thermal pad area but
under the package.
REQUIRED:
Thermal pad area 2.286mm x 2.286mm
(90 mils x 90 mils) with 5 vias
(via diameter = 13 mils)
Figure 10. 8-Pin PowerPAD PCB Etch and Via
Pattern
3. Place the recommended number of plated-through
holes (or thermal vias) in the area of the thermal pad.
These holes should be 13 mils in diameter. They are kept
small so that solder wicking through the holes is not a
problem during reflow. The minimum recommended
number of holes for the SO-8 PowerPAD package is 5, as
shown in Figure 10.
16
Solid Via
RECOMMENDED
Web or Spoke Via
NOT RECOMMENDED
(due to poor heat conduction)
Figure 11. Via Connection
7. The top-side solder mask should leave the pad
connections and the thermal pad area exposed. The
thermal pad area should leave the 13 mil holes exposed.
The larger holes outside the thermal pad area may be
covered with solder mask.
8. Apply solder paste to the exposed thermal pad area and
all of the package terminals.
9. With these preparatory steps in place, the PowerPAD IC
is simply placed in position and run through the solder
reflow operation as any standard surface-mount
component. This results in a part that is properly installed.
For detailed information on the PowerPAD package
including thermal modeling considerations and repair
procedures, please see Technical Brief SLMA002,
PowerPAD Thermally Enhanced Package, located at
www.ti.com.