LP2998MRX Datasheet, PDF (16/26 Pages) Texas Instruments – LP2998 DDR-I and DDR-II Termination Regulator

LP2998
SNVS521I – DECEMBER 2007 – REVISED APRIL 2013
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OUTPUT CAPACITOR SELECTION
For applications utilizing the LP2998 to terminate SSTL-2 I/O signals the typical application circuit shown in
Figure 27 can be implemented.
SD
AV_IN = 2.5V
V_DDQ = 1.8V
+
C_IN
LP2998
SD
AV_IN
V_REF
V_DDQ
VSENSE
PV_IN
V_TT
GND
+
C_REF
V_REF = 0.9V
+
C_OUT
V_TT = 0.9V
Figure 27. Typical SSTL-2 Application Circuit
This circuit permits termination in a minimum amount of board space and component count. Capacitor selection
can be varied depending on the number of lines terminated and the maximum load transient. However, with
motherboards and other applications where V_TT is distributed across a long plane, it is recommended to use
multiple bulk capacitors in addition to high frequency decoupling. Figure 28 depicts an example circuit where 2
bulk output capacitors could be situated at both ends of the V_TT plane for optimal placement. Large aluminum
electrolytic capacitors are typically used for their low ESR and low cost.
SD
V_DDQ = 2.5V
V_DD = 2.5V
+
47 PF
LP2998
SD
V_DDQ
V_REF
AV_IN
V_SENSE
PV_IN
V_TT
GND
V_REF = 1.25V
+
0.01 PF
+
330 PF
V_TT = 1.25V
+
330 PF
Figure 28. Typical SSTL-2 Application Circuit for Motherboards
In most PC applications, an extensive amount of decoupling is required because of the long interconnects
encountered with the DDR-SDRAM DIMMs mounted on modules. As a result, bulk aluminum electrolytic
capacitors in the range of 1000uF are typically used.
PCB Layout Considerations
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. V_SENSE should be connected to the V_TT termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
3. V_DDQ can be connected remotely to the V_DDQ rail input at either the DIMM or the Chipset. This provides the
most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from the
package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these
can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the V_SENSE trace to avoid noise pickup from switching I/O signals. A
0.1uF ceramic capacitor located close to the _SENSE can also be used to filter any unwanted high frequency
signal. This can be an issue especially if long _SENSE traces are used.
6. V_REF should be bypassed with a 0.01 µF or 0.1 µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the V_REF pin.
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