BQ4845 Datasheet, PDF (16/22 Pages) Texas Instruments – Parallel RTC With CPU Supervisor

bq4845/bq4845Y
Power-Down/Power-Up Timing (TA = TOPR)
Symbol
tF
tFS
tR
tPF
tWPT
tCSR
tRST
tCER
tCED
Parameter
Minimum
VCC slew from 4.75 to
300
4.25V
VCC slew from 4.25 to VSO 10
VCC slew from VSO to
VPFD(MAX)
100
Interrupt delay from
6
VPFD
Write-protect time for
90
external RAM
CS at VIH after power-up
VPFD to RST inactive
100
tCSR
Chip enable recovery
time
tCSR
Chip enable propagation
delay to external SRAM
-
Typical
-
-
-
-
100
200
-
-
9
Maximum
-
-
-
24
125
300
tCSR
tCSR
12
Unit
µs
µs
µs
µs
µs
ms
ms
ms
ns
Conditions
Delay after VCC slews down past
VPFD before SRAM is write-protected
and RST activated.
Internal write-protection period af-
ter VCC passes VPFD on power-up.
Reset active time-out period
Time during which external SRAM
is write-protected after VCC passes
VPFD on power-up.
Output load A
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Notes:
PWRIE set to “1” to enable power fail interrupt.
RST and INT are open drain and require an external pull-up resistor.
16
Aug. 1995