BQ4845 Datasheet, PDF (1/22 Pages) Texas Instruments – Parallel RTC With CPU Supervisor

bq4845/bq4845Y
Parallel RTC With CPU Supervisor
Features
® Real-Time Clock counts seconds
through years in BCD format
® On-chip battery-backup switchover
circuit with nonvolatile control for
external SRAM
® Less than 500nA of clock opera-
tion current in backup mode
® Microprocessor reset valid to
VCC = VSS
® Independent watchdog timer
with a programmable time-out
period
® Power-fail interrupt warning
® Programmable clock alarm inter-
rupt active in battery-backup
mode
® Programmable periodic interrupt
® Battery-low warning
General Description
The bq4845 Real-Time Clock is a
low-power microprocessor periph-
eral that integrates a time-of-day
clock, a 100-year calendar, and a
CPU supervisor in a 28-pin SOIC or
DIP. The bq4845 is ideal for fax ma-
chines, copiers, industrial control
systems, point-of-sale terminals,
data loggers, and computers.
The bq4845 provides direct connec-
tions for a 32.768KHz quartz crystal
and a 3V backup battery. Through
the use of the conditional chip en-
able output (CEOUT) and battery
voltage output (VOUT) pins, the
bq4845 can write-protect and make
nonvolatile external SRAMs. The
backup cell powers the real-time
clock and maintains SRAM infor-
mation in the absence of system
voltage.
The bq4845 contains a temperature-
compensated reference and comparator
circuit that monitors the status of its
voltage supply. When the bq4845 de-
tects an out-of-tolerance condition, it
generates an interrupt warning and
subsequently a microprocessor reset.
The reset stays active for 200ms after
VCC rises within tolerance, to allow for
power supply and processor stabiliza-
tion.
The bq4845 also has a built-in
watchdog timer to monitor processor
operation. If the microprocessor does
not toggle the watchdog input (WDI)
within the programmed time-out pe-
riod, the bq4845 asserts WDO and
RST. WDI unconnected disables the
watchdog timer.
The bq4845 can generate other in-
terrupts based on a clock alarm con-
dition or a periodic setting. The
alarm interrupt can be set to occur
from once per second to once per
month. The alarm can be made active
in the battery-backup mode to serve
as a system wake-up call. For inter-
rupts at a rate beyond once per sec-
ond, the periodic interrupt can be pro-
grammed with periods of 30.5µs to
500ms.
Pin Connections
V_OUT 1
X₁ 2
X₂ 3
WDO 4
INT 5
RST 6
A₃ 7
A₂ 8
A₁ 9
A₀ 10
DQ₀ 11
DQ₁ 12
DQ₂ 13
V_SS 14
28 V_CC
27 WE
26 CE_IN
25 CEOUT
24 BC
23 WDI
22 OE
21 CS
20 V_SS
19 DQ₇
18 DQ8
17 DQ₅
16 DQ₄
15 DQ₃
28-DIP or SOIC
PN484501.eps
Aug. 1995
Pin Names
A0–A3
Clock/control address
inputs
DQ0–DQ7 Data inputs/outputs
WE
Write enable
OE
Output enable
CS
Chip select input
CEIN
External RAM chip
enable
CEOUT
Conditional RAM chip
enable
X1–X2 Crystal inputs
1
BC
VOUT
INT
RST
WDI
WDO
VCC
VSS
Backup battery input
Back-up battery output
Interrupt output
Microprocessor reset
Watchdog input
Watchdog output
+5V supply
Ground