LP38856_15 Datasheet, PDF (15/24 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator With Enable

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10 Layout
LP38856
SNVS336F – JUNE 2006 – REVISED AUGUST 2015
10.1 Layout Guidelines
Good layout practices will minimize voltage error and prevent instability which can result from ground loops. The
input and output capacitors must be directly connected to the device pins with short traces that have no other
current flowing in them (Kelvin connect).
The best way to do this is to place the capacitors very near the device and make connections directly to the
device pins via short traces on the top layer of the PCB. The regulator’s ground pin must be connected through
vias to the internal or backside ground plane so that the regulator has a single point ground.
The external resistors which set the output voltage must also be located very near the device with all connections
directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the
load point or DC error will be induced.
10.2 Layout Example
V_IN
C_IN
C_OUT
V_OUT
EN
IN
C_BIAS
GND
OUT
BIAS
Figure 26. LP38856 Layout Example
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