LP38856_15 Datasheet, PDF (13/24 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator With Enable

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LP38856
SNVS336F – JUNE 2006 – REVISED AUGUST 2015
Tantalum capacitors will also provide stable operation across the entire operating temperature range. However,
the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum
recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, tantalum and/or aluminum,
to be added in parallel.
8.2.2.1.2 Input Capacitor
The input capacitor must be at least 10 µF, but can be increased without limit. Its purpose is to provide a low
source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended.
Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor
(the lower, the better).
Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at
cold temperatures. They are not recommended for any application where the ambient temperature falls below
0°C.
8.2.2.1.3 Bias Capacitor
The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is
recommended).
8.2.2.2 Power Dissipation and Heatsinking
A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature
of the application. Under all possible conditions, the junction temperature must be within the range specified
under operating conditions.
The total power dissipation of the device is the sum of three different points of dissipation in the device.
The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula:
P_D(PASS) = (V_IN - V_OUT) × I_OUT
(1)
The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the
formula:
P_D(BIAS) = V_BIAS × I_GND(BIAS)
where
• I_GND(BIAS) is the portion of the operating ground current of the device that is related to V_BIAS.
(2)
The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with
the formula:
P_D(IN) = V_IN × I_GND(IN)
where
• I_GND(IN) is the portion of the operating ground current of the device that is related to V_IN.
(3)
The total power dissipation is then:
P_D = P_D(PASS) + P_D(BIAS) + P_D(IN)
(4)
The maximum allowable junction temperature rise (ΔT_J) depends on the maximum anticipated ambient
temperature (T_A(MAX)) for the application, and the maximum allowable operating junction temperature (T_J(MAX)):
ΔT_J = T_J(MAX) – T_A(MAX)
(5)
The maximum allowable value for junction to ambient thermal resistance, R_θJA, can be calculated using the
formula:
R_θJA ≤ ΔT_J / P_D
(6)
The LP38856 is available in TO-220 and DDPAK/TO-263 packages. The thermal resistance in the application
depends on amount of copper area or heat-sink, and on air flow. If the maximum allowable value of R _θJA
calculated above is ≥ 32°C/W for TO-220 package and ≥ 41°C/W for DDPAK/TO-263 package no heat-sink is
needed because the package alone can dissipate enough heat to satisfy these requirements. If the value needed
for allowable R_θJA falls below these limits, a heat-sink is required.
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