LP38856_15 Datasheet, PDF (11/24 Pages) Texas Instruments – 3A Fast-Response High-Accuracy LDO Linear Regulator With Enable

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LP38856
SNVS336F – JUNE 2006 – REVISED AUGUST 2015
Feature Description (continued)
7.3.3 Bias Voltage
The bias voltage (V_BIAS) is a low current external voltage rail required to bias the control circuitry and provide
gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3 V to 5.5 V to ensure proper
operation of the device.
7.3.4 Undervoltage Lockout
The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is
below the undervoltage lock-out (UVLO) threshold of approximately 2.45 V.
As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is
approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.
When the bias voltage is between the UVLO threshold and the minimum operating rating value of 3 V the device
will be functional, but the operating parameters will not be within the specified limits.
7.3.5 Supply Sequencing
There is no requirement for the order that V_IN or V_BIAS are applied or removed. However, the output voltage
cannot be specified until both V_IN and V_BIAS are within the range of specified operating values.
If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be
diode clamped to ground. A Schottky diode is recommend for this diode clamp.
7.3.6 Reverse Voltage
A reverse voltage condition will exist when the voltage at the OUT pin is higher than the voltage at the input pin.
Typically this will happen when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed.
The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass
element is not driven, there will not be any reverse current flow through the pass element during a reverse
voltage event. The gate of the pass element is not driven when V_BIAS is below the UVLO threshold.
When V_BIAS is above the UVLO threshold the control circuitry is active and will attempt to regulate the output
voltage. Because the input voltage is less than the output voltage, the control circuit will drive the gate of the
pass element to the full V_BIAS potential when the output voltage begins to fall. In this condition, reverse current
will flow from the OUT pin to the IN pin, limited only by the R_DS(ON) of the pass element and the output-to-input
voltage differential. This condition is outside the specified operating range and must be avoided.
7.4 Device Functional Modes
7.4.1 Operation with 3 V ≤ V_BIAS ≤ 5.5 V , V_OUT(TARGET) + 0.3 V ≤ V_IN ≤ V_BIAS
The device operates if the bias voltage is equal to, or exceeds, 3 V; input voltage is equal to, or exceeds,
V_OUT(TARGET) + 0.3 V. At bias voltages below the minimum V_BIAS requirement, the device does not operate
correctly, and output voltage may not reach target value.
7.4.2 Operation with V_EN Control
If the voltage on the EN pin is less than 1 V, the device is disabled. Raising V_EN above 1.5 V initiates the start-up
sequence of the device.
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