DRV8307_15 Datasheet, PDF (15/34 Pages) Texas Instruments – DRV8307 Brushless DC Motor Controller

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DRV8307
SLVSCK2 – APRIL 2014
When the motor is braking, all low-side drivers are held in an on state, causing all low-side FETs to turn on.
8.3.6 Output Pre-Drivers
The output drivers for each phase consist of N-channel and P-channel MOSFET devices arranged as a CMOS
buffer. They are designed to directly drive the gate of external N-channel power MOSFETs. The outputs provide
synchronous rectification operation. In synchronous rectification, the low-side FET is turned on when the high
side is turned off.
The high-side gate drive output UHSG is driven to VCP whenever the duty cycle output U_PD from the PWM
generator is high, the enable signal U_HS from the commutation logic is active, and the current limit (V_LIMITER) is
not active. If the high-side FET is on and a current limit event occurs, the high-side FET is immediately turned off
until the next PWM cycle.
The low-side gate drive ULSG is driven to VM whenever the internal signal U_LS is high, or whenever
synchronous rectification is active and UHSG is low.
Phases V and W operate in an identical fashion.
VCP
UHGS
U_PD
ILIMIT
U_LS
BRAKE
To Other
Phases
Dead
Time
Generator
and
Drive
Logic
VM
11 V
U
ULSG
Figure 7. Pre-Driver Block Diagram
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