TMS320F28069_12 Datasheet, PDF (146/174 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
GPIOLMPSEL
LPMCR0
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
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GPIOx pin
Low P ower
Modes Block
External Interrupt
PIE
MUX
Asynchronous
path
GPxPUD
Internal
Pullup
GPxQSEL1/2
GPxCTRL
Input
Qualification
Asynchronous path
High Impedance
Output Control
0 = Input, 1 = Output
XRS
GPxDAT (read)
00 N/C
01 ^{Peripheral 1 Input}
10 Peripheral 2 Input
11 _{Peripheral 3 Input}
GPxTOGGLE
GPxCLEAR
GPxSET
00
GPxDAT (latch)
01
Peripheral 1 Output
10 Peripheral 2 Output
11 Peripheral 3 Output
00
GPxDIR (latch)
01 Peripheral 1 Output Enable
10 Peripheral 2 Output Enable
11
Peripheral 3 Output Enable
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the "Systems
Control and Interrupts" chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number
SPRUH18) for pin-specific variations.
Figure 5-49. GPIO Multiplexing
146 Peripheral and Electrical Specifications
Copyright © 2010–2012, Texas Instruments Incorporated
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TMS320F28064 TMS320F28063 TMS320F28062