TMS320F28069_12 Datasheet, PDF (118/174 Pages) Texas Instruments – Piccolo Microcontrollers

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
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Table 5-44. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
NO.
M58 t_su(DRV-CKXL)
M59 t_h(CKXL-DRV)
M60 t_su(FXL-CKXL)
M61 t_c(CKX)
(1) 2P = 1/CLKG
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
MASTER
MIN MAX
30
1
2P ⁽¹⁾
SLAVE
MIN MAX
8P – 10
8P – 10
16P + 10
16P
UNIT
ns
ns
ns
ns
Table 5-45. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)⁽¹⁾
over recommended operating conditions (unless otherwise noted)
NO.
PARAMETER
MASTER
MIN
MAX
SLAVE
UNIT
MIN
MAX
M53
M54
M55
M56
t_h(CKXH-FXL)
t_d(FXL-CKXL)
t_d(CLKXH-DXV)
t_{dis(CKXH-DXHZ)}
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
Disable time, DX high impedance following last
data bit from CLKX high
P
2P ⁽¹⁾
–2
P+6
ns
ns
0
3P + 6 5P + 20 ns
7P + 6
ns
M57 t_d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
(1) 2P = 1/CLKG
For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Also CLKG should be LSPCLK/2
by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 90 MHz, CLKX maximum frequency
is LSPCLK/16 , that is 5.625 MHz and P = 11.11 ns.
CLKX
FSX
DX
DR
LSB
M60
MSB
M61
M53
M54
M56
Bit 0
Bit 0
M57
M58
Bit(n-1)
Bit(n-1)
M55
(n-2)
M59
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5-38. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
118 Peripheral and Electrical Specifications
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