TMS320DM357 Datasheet, PDF (146/195 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM357
Digital Media System-on-Chip
SPRS553 – NOVEMBER 2008
www.ti.com
Table 6-52. Timing Requirements for VPBE Control Input With Respect to PCLK and VPBECLK⁽¹⁾ (see
Figure 6-33)
-270
NO.
UNIT
MIN
MAX
9
t_{su(VCTLV-PCLK)}
Setup time, VCTL valid before PCLK edge
10
t_{h(PCLK-VCTLV)}
Hold time, VCTL valid after PCLK edge
27 t_{su(VCTLV-VPBECLK)} Setup time, VCTL valid before VPBECLK rising edge
28 t_{h(VPBECLK-VCTLV)} Hold time, VCTL valid after VPBECLK rising edge
33
t_{su(FIELD-PCLK)}
Setup time, LCD_FIELD valid before PCLK edge
34
t_{h(PCLK-FIELD)}
Hold time, LCD_FIELD valid after PCLK edge
35 t_{su(FIELD-VPBECLK)} Setup time, LCD_FIELD valid before VPBECLK edge
36
t_{h(VPBECLK-FIELD)}
Hold time, LCD_FIELD valid after VPBECLK edge
2
ns
0.5
ns
2
ns
0.5
ns
5P ⁽²⁾
ns
5P ⁽²⁾
ns
5P ⁽²⁾
ns
5P ⁽²⁾
ns
(1) PCLK may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the rising
edge of PCLK is referenced. When in negative edge clocking mode, the falling edge of PCLK is referenced.
(2) P = 1/(VCLKIN clock frequency) in ns. VCLKIN is either PCLK or VPBECLK, whichever is used.
VPBECLK
PCLK
(Positive Edge Clocking)
PCLK
(Negative Edge Clocking)
10
9
28
27
VCTL^(A)
34
33
36
35
LCD_FIELD
A. VCTL = HSYNC and VSYNC
Figure 6-33. VPBE Input Timing With Respect to PCLK and VPBECLK
146 Peripheral and Electrical Specifications
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