TMS320DM357 Datasheet, PDF (1/195 Pages) Texas Instruments – Digital Media System-on-Chip

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1 Digital Media System-on-Chip (DMSoC)
TMS320DM357
Digital Media System-on-Chip
SPRS553 – NOVEMBER 2008
1.1 Features
• High-Performance Digital Media SoC
– 270-MHz ARM926EJ-S™ Core
– Fully Software-Compatible With ARM9™
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 16K-Byte RAM
– 8K-Byte ROM
• H.264/MPEG4/JPEG Coprocessor
– Fixed Function Coprocessor Supports:
• H.264 BP Codec at D1, VGA, SIF
• MPEG4 SP Codec at D1, VGA, SIF
• JPEG Codec
• Embedded Trace Buffer™ (ETB11™) With 4KB
Memory for ARM9 Debug
• Endianness: Little Endian
• Video Processing Subsystem
– Front End Provides:
• CCD and CMOS Imager Interface
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
• Preview Engine for Real-Time Image
Processing
• Glueless Interface to Common Video
Decoders
• Histogram Module
• Auto-Exposure, Auto-White Balance and
Auto-Focus Module
• Resize Engine
– Resize Images From 1/4x to 4x
– Separate Horizontal/Vertical Control
– Back End Provides:
• Hardware On-Screen Display (OSD)
• 3 - 54-MHz DACs for a Combination of:
– Composite NTSC/PAL Video
– Luma/Chroma Separate Video
(S-video)
– Component (YPbPr or RGB) Video
(Progressive/Interlaced)
– Digital Output
– 8-/16-bit YUV or up to 24-Bit RGB
– Up to 2 Video Windows
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
– Asynchronous 16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
• Flash Memory Interfaces
– NOR (8-/16-Bit-Wide Data)
– NAND (8-/16-Bit-Wide Data)
• Flash Card Interfaces
– Multimedia Card (MMC)/Secure Digital (SD)
with Secure Data I/O (SDIO)
– SmartMedia
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Three UARTs (One with RTS and CTS Flow
Control)
• One Serial Peripheral Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• Audio Serial Port (ASP)
– I2S
– AC97 Audio Codec Interface
– Standard Voice Codec Interface (AIC12)
• 10/100 Mb/s Ethernet Media Access Controller
(EMAC)
– IEEE 802.3 Compliant
– Media Independent Interface (MII)
• Host Port Interface (HPI) with 16-Bit
Multiplexed Address/Data
• USB2.0 OTG Controller With Integrated
High-Speed 2.0 PHY
• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash or UART
• Comprehensive Power-Saving Modes
• Flexible PLL Clock Generators
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