TMS320DM357 Datasheet, PDF (128/195 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM357
Digital Media System-on-Chip
SPRS553 – NOVEMBER 2008
www.ti.com
6.12 Video Processing Sub-System (VPSS) Overview
The DM357 Video Processing Sub-System (VPSS) provides a Video Processing Front End (VPFE) input
interface for external imaging peripherals (i.e., image sensors, video decoders, etc.) and a Video
Processing Back End (VPBE) output interface for display devices, such as analog SDTV displays, digital
LCD panels, HDTV video encoders, etc.
Note: The VPSS module is supported with Linux Application Peripheral Interfaces (APIs) commonly used
by video application developers. Video for Linux 2 or V4L2 uses APIs commonly used for video capture.
The typical use cases of the VPSS Video Front-End (VPFE) have been ported to this Linux API structure.
The VPSS Back-End (VPBE) uses FBDev/DirectFB as the APIs.
The VPSS register memory mapping is shown in Table 6-37.
HEX ADDRESS
RANGE
0x01C7 3400
0x01C7 3404
0x01C7 3408
0x01C7 3508
0x01C7 350C -
0x01C7 3FFF
Table 6-37. VPSS Register Descriptions
REGISTER ACRONYM
PID
PCR
-
SDR_REG_EXP
-
DESCRIPTION
Peripheral Revision and Class Information
VPSS Control Register
Reserved
SDRAM Non Real-Time Read Request Expand
Reserved
To ensure NTSC- and PAL-compliant output video, the stability of the input clock source is very important.
TI recommends a 27-MHz, 50-ppm crystal. Ceramic oscillators are not recommended. The NTSC/PAL
color sub-carrier frequency is derived from the 27-MHz clock. Therefore, if the 27-MHz clock drifts, then
the color sub-carrier frequency will drift as well. Assuming no 27-MHz frequency drift, the color sub-carrier
frequency is generated as follows:
f_{sc -ntsc}
=
27 MHz
çæ ³⁵ ÷ö
è ²⁶⁴ ø
= 3.5795454545
MHz
f_{sc -pal}
=
27 MHz çæ ¹⁶⁷ ÷ö
è ¹⁰¹⁷ ø
=
4.4332628318
MHz
To ensure the color sub-carrier frequency will not drift out of spec, the user must follow the crystal
requirements discussed in Section 6.5.1, Clock Input Option 1 – Crystal or Ceramic Resonator.
Alternatively, if the VPBE input clock is sourced from the VPBECLK or VPFE clock inputs, these clocks
must have a frequency stability of ± 50 ppm to ensure the NTSC and PAL compliant output video.
128 Peripheral and Electrical Specifications
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