TLC320AD58C Datasheet, PDF (14/27 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

Several modes are available when the TLC320AD58C is configured as a slave. Using the Mode0, Mode1,
and Mode2 terminals, the TLC320AD58C can be set to shift out the MSB first or the LSB first [see Figures
2–4(a) and 2–4(b)]. The number of bits shifted out, however, can be controlled by the number of valid SCLK
cycles provided within the left or right channel period. If only enough clocks are provided to shift out 16 data
bits before LRClk changes state, then this is equivalent to a 16-bit mode. Modes 1 and 2 both require 64
SCLK periods per LRClk period.
Mode 000
SCLK
Fsync
DOUT
input
input
output
LRClk input
(a) 18-BIT SLAVE MODE (Fsync high)
17 16 . . . 1 0
Left
17 16 . . . 1 0
32 – 128 SCLKs
Right
Mode 001
SCLK
Fsync
DOUT
LRClk
Mode 010
SCLK
Fsync_1
DOUT_1
Fsync_2
DOUT_2
LRClk
(b) 18-BIT SLAVE MODE (Fsync high)
0 1 . . . 16 17
64 SCLKs
Left
Right
(c) 18-BIT SLAVE MODE (Fsync controlled)
0 1 . . . 16 17
17
...
0
17
...
0
17
Left
...
0
17
32 – 128 SCLKs
Right
...
0
Figure 2–4. Serial Slave Transfer Modes
2–6