TLC320AD58C Datasheet, PDF (11/27 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

2.3 Sigma-Delta Modulator
The modulator is a fourth-order sigma-delta modulator with 64 times oversampling. The ADC provides
high-resolution, low-noise performance from a one-bit converter using oversampling techniques.
2.4 Decimation Filter
The decimation filter used after the sigma-delta modulator reduces the digital data rate to the sampling rate
of LRClk. This is accomplished by decimating with a ratio of 1:64. The output of this filter is a 2s complement
data word of up to 18 bits serially clocked out.
If the input value exceeds the full range of the converter, the output of the decimator is held at the appropriate
extreme until the input returns to the dynamic range of this device.
2.5 High-Pass Filter
The high-pass filter removes dc from the input.
2.6 Master-Clock Circuit
The master-clock circuit is used to generate and distribute necessary clocks throughout the device. MCLK
is the external master clock input. CMODE is used to select the relationship of MCLK to the sample rate of
LRClk. When CMODE is low, the sample rate of the data paths is set as LRClk = MCLK/256. When CMODE
is high, the sample rate is set as LRClk = MCLK/384. With a fixed oversampling ratio of 64×, the effect of
changing MCLK is shown in Table 2–1.
When the TLC320AD58C is in master mode, SCLK is derived from MCLK in order to provide clocking of
the serial communications between the sigma-delta audio ADC and a digital signal processor (DSP) or
control logic. This is equivalent to a clock running at 64 × LRClk.
When the TLC320AD58C is in slave mode, SCLK is externally derived.
Table 2–1. Master-Clock to Sample-Rate Comparison
(Modes 1, 3, 4, 5)
MCLK
(MHz)
CMODE
SCLK
(MHz)
LRClk
(kHz)
12.2880
18.4320
11.2896
16.9344
8.1920
12.2880
0.2560
0.3840
Low
3.0720
48
High
Low
2.8224
44.1
High
Low
2.0480
32
High
Low
0.0640
1
High
2.7 Test
TEST1 and TEST2 are reserved for factory test and should be tied to digital ground (DV_SS).
2.8 Serial Interface
Although the serial data is shifted out in two seperate time packets that represent the left and right channels,
the inputs are sampled and converted simultaneously.
The serial interface protocol has master and slave modes each with different read out modes. The master
mode is used to source the control signals for conversion synchronization, while the slave mode allows an
external controller to provide conversion synchronization signals.
The five master modes are shown in Figures 2–3(a) through 2–3(e), and the three slave modes are shown
in Figures 2–4(a) through 2–4(c). For a 16-bit word, D15 is the most significant bit and D0 is the least
significant bit. Unless otherwise specified, all values are in 2s complement format.
2–3