TLC320AD58C Datasheet, PDF (12/27 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

In master mode, SCLK is generated internally and is sourced as an output. The relationship of SCLK to
LRClk is 64× (modes 1, 3, 4, 5) or 32× (modes 6, 7). In slave mode, SCLK is an input. SCLK timing must
meet the timing specifications shown in the recommended operating conditions section.
2.8.1 Master Mode
As the master, the TLC320AD58C generates LRClk, Fsync, and SCLK from MCLK. These signals are
provided for synchronizing the serial port of a digital signal processor (DSP) or other control devices.
Fsync is used to designate the valid data from the ADC, and this is accomplished in the master modes by
one of two methods. The first is a single pulse on Fsync prior to valid data. This indicates the starting point
for the data. The second method of frame synchronization is to hold Fsync high during the entire valid data
cycle, which provides boundaries for the data.
LRClk is generated internally from MCLK. The frequency of this signal is fixed at the sampling frequency
f_s [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)]. During the high period of this signal, the left
channel data is serially shifted to the output; during the low period, the right channel data is shifted to the
output. The conversion cycle is synchronized with the rising edge of LRClk.
Five modes are available when the device is configured as a master. Two modes are for 18-bit
communications. These modes differ from each other in that the MSB is transferred first in one mode while
the LSB is transferred first in the second mode [see Figures 2–3(b) and 2–3(c)]. When the LSB is transferred
first, the data is right justified to the LRClk [see Figures 2–3(a) through 2–3(e)]. The three other master
modes are 16-bit modes. Once again, two of the modes differ as MSB first versus LSB first. These two
modes set SCLK = LRClk × 32. This is half the frequency used in the other transfer modes [see
Figures 2–3(d) and 2–3(e)]. The third 16-bit mode provides the data MSB first with one clock delay after
LRClk [see Figure 2–3(a)].
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