LP38691_15 Datasheet, PDF (14/34 Pages) Texas Instruments – LP3869x/-Q1 500-mA Low-Dropout CMOS Linear Regulators Stable With Ceramic Output Capacitors

LP38691, LP38693, LP38691-Q1, LP38693-Q1
SNVS321N – JANUARY 2005 – REVISED MARCH 2015
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Reverse Voltage
A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin.
Typically this will happen when V_IN is abruptly taken low and C_OUT continues to hold a sufficient charge such that
the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is
connected to the output.
There are two possible paths for current to flow from the OUT pin back to IN during a reverse voltage condition.
1. While V_IN is high enough to keep the control circuity alive, and the EN pin (LP38693 only) is above the
V_EN(ON) threshold, the control circuitry will attempt to regulate the output voltage. If the input voltage is less
than the programmed output voltage, the control circuit will drive the gate of the pass element to the full ON
condition. In this condition, reverse current will flow from the OUT to the IN pin, limited only by the R_DS(ON) of
the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF
in this manner will not damage the device as the current will rapidly decay. However, continuous reverse
current should be avoided. When the EN pin is low, this condition will be prevented.
2. The internal PFET pass element has an inherent parasitic diode. During normal operation, the input voltage
is higher than the output voltage and the parasitic diode is reverse biased. However, when V_IN is below the
value where the control circuity is alive, or the EN pin is low (LP38693 only), and the output voltage is more
than 500 mV (typical) above the input voltage the parasitic diode becomes forward biased and current flows
from the output pin to the input pin through the diode. The current in the parasitic diode should be limited to
less than 1 A continuous and 5 A peak.
If used in a dual-supply system where the regulator output load is returned to a negative supply, the output
pin must be diode clamped to ground to limit the negative voltage transition. A Schottky diode is
recommended for this protective clamp.
9.2 Typical Application
V_IN
1 µF *
IN
OUT
LP38691
SNS^**
GND
V_OUT
V_IN
1 µF *
V_EN
1 µF *
IN
OUT
EN
LP38693
SNS^**
GND
V_OUT
1 µF *
* Minimum value required for stability.
**WSON package devices only.
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