BQ27210 Datasheet, PDF (13/30 Pages) Texas Instruments – Li-Ion AND Li-Pol BATTERY GAS GAUGE IC FOR PORTABLE APPLICATIONS (bqJUNIOR)

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bq27010, bq27210
SLUS707B – APRIL 2006 – REVISED JANUARY 2007
APPLICATION INFORMATION
Control and MODE Registers (CTRL/MODE) — Address 0x00/0x01
The device control register is used by the host system to request special operations by the bqJUNIOR. The
highest priority command set in the MODE register is performed when the host writes data 0xA9, 0x56, or 0xC5
as indicated to the control register. The CTRL register and MODE bits 5, 4, 3, 1, and 0 are cleared when the
command is accepted. The host must set the appropriate command bit in MODE before sending the command
key to CTRL.
Mode Register (MODE) — Address 0x01
COMMAND KEY = 0xA9
COMMAND KEY = 0x56
COMMAND KEY = 0xC5
BIT 7
GPIEN
GPIEN
GPIEN
BIT 6
GPSTAT
GPSTAT
GPSTAT
BIT 5
WRTNAC
CEO
UPDC
BIT 4
DONE
CIO
UPEDVI
BIT 3
PRST
WNACCI
UPDMF
BIT 2
INIT
INIT
INIT
BIT 1
FRST
WRTCYC
UPCFG
BIT 0
SHIP ⁽¹⁾
WRTLMD
UPCOMP
(1) bq27010 only
GPIEN
GPIEN sets the state of the GPIO pin. A 1 configures the GPIO pin as input, while a 0 configures
the GPIO pin as an open-drain output. This bit is initialized to the value of bit 7 of the PKCFG
register in the EEPROM. The user should keep this bit set or cleared as desired when other bits in
this register are written.
GPSTAT
GPSTAT sets the state of the open drain output of the GPIO pin (GPIEN = 0). A 1 turns off the
open drain output, while a 0 turns the output on. This bit is set to 1 on POR. When the GPIO pin is
an input (GPIEN=1), this bit returns the logic state of the GPIO pin. The user should keep this bit
set or cleared as desired when other bits in this register are written.
WRTNAC
WRTNAC is used to transfer data from the AR registers to NAC. Other registers are updated as
appropriate. This command is useful during the pack manufacture and test to initialize the gauge to
match the estimated battery capacity.
DONE
DONE is used to write NAC equal to LMD. Useful if the host uses a charge termination method
that does not allow the monitor to detect the taper current. The host system could use this
command when the charging is complete to force update of internal registers to a full battery
condition.
PRST
Partial reset. This command requests a reset of all RAM registers except NAC, LMD, and the CI bit
in FLAGS. This command is intended for manufacturing use.
INIT
The INIT status bit is set to 1 by the bqJUNIOR if there is a full reset or if data corruption is
detected in the internal memory containing EEPROM coefficients. Either of these events will cause
the bqJUNIOR to update internal memory values. If NAC, LMD, CYCT, or EEPROM-initialized
coefficients need to be modified from their original values, the host should first update the values
and then clear the INIT bit. The INIT bit is not cleared by the bqJUNIOR.
FRST
Full reset. This command bit requests a full reset. A full reset reinitializes all RAM registers,
including the NAC, LMD, and FLAGS registers. This command is intended for manufacturing use.
SHIP
This command bit requests that the device (bq27010 only) should be put in ship mode. See the
Power Mode section for a description of the ship mode. This command is intended for
manufacturing use.
CEO
This command bit requests that the external offset value is measured. Care should be taken to
insure that no charge or discharge current flows during the time this measurement is made. The
external offset value is the total offset of the DSCC plus any external PCB affects. The result can
be read in 0x5f-5e. The result is a signed number with an LSB value of 1.225 µV. The command
takes approximately 5.5 seconds to make the measurement. This command is intended for
manufacturing use. The CIO offset value may be subtracted from the CEO offset value to
determine the external board offset. This value can be programmed into PKCFG[4:2] in the
EEPROM for automatic compensation of this external offset value.
CIO
This command bit requests that the internal offset value is measured. The internal offset value is
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