BQ25040 Datasheet, PDF (13/25 Pages) Texas Instruments – 1.1A, Single-Input, Single Cell Li-Ion Battery Charger With 50mA LDO and 2.3A Production Test Support

bq25040
www.ti.com ...................................................................................................................................................... SLUS910B – MARCH 2009 – REVISED MARCH 2009
Single Input Interface (EN/SET)
EN/SET is used to enable/disable the device as well as select the input current limit and Production Test mode.
EN/SET is pulled low to enable the device. After the 50µs deglitch expires, the IC enters the 32ms WAIT state.
EN/SET may be used to program the current limit during this time. Once t_WAIT expires, the IC starts up. If no
command is sent to EN/SET during t_WAIT, the IC starts up in USB500 mode.
Programming the different modes is done by pulsing the EN/SET input. See Table 1 for a map of the different
modes. A valid high pulse is between 100µs and 700µs. The time between pulses must be between 100µs and
700µs to be properly read. Once EN/SET is held low for 1.5ms, the number of pulses is passed to the control
logic and decoded and then the mode changes. If during the pulse counting, more than 3 pulses occur, the
USB100 mode is immediately selected on the fourth pulse, and the 1.5ms timer does not have to expire. See
Figure 22 for a flow diagram of the EN/SET interface.
Once a mode has been programmed once, further pulses on EN/SET are ignored until power is toggled, or the
device is disabled and then enabled.
Table 1. Pulse Counting Map for EN/SET Interface
NO. OF PULSES
0
1
2
3
≥4
MODE CONTROL
Current Limit
Current Limit
Current Limit
Production Test Mode
Current Limit
VALUE
USB500 Mode
(default for startup)
ISET Programmed
USB100 Mode
Enabled
USB100 Mode
If, at any time, the EN/SET input is held high for more than 1.5ms, the IC is disabled. When disabled, charging is
suspended and the bq25040 input quiescent current is reduced.
BITs decoded once EN/SET
pulled low for 1.5ms
Charge disabled if EN/SET
pulled high for >1.5ms
EN/SET
IC can be
programmed during
t_WAIT
t_HIGH
t_DGL
1.5 ms
Additional pulses on EN/SET
ignored after mode programmed
1.5 ms
I_BAT
t_WAIT
t_LOW
USB500
USB100
Figure 22. EN/SET Timing Diagram
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :bq25040
Submit Documentation Feedback
13