TLC770X Datasheet, PDF (12/27 Pages) Texas Instruments – BiCMOS SUPPLY VOLTAGE SUPERVISORS

Capacitors of 1000 µF and more having sufficiently low leakage current can be used. With a capacitance
C_t = 1000 µF, the maximum delay time which results is then:
t_d = 2.1⋅ 10⁴ ⋅ 1000 µF = 21 s
Smaller values than 100 pF for the capacitance C_t do not appear to be advisable, since the effective capacitance is
then increasingly influenced by the parasitic capacitance of the module, and a larger departure of the actual delay
time t_d from the calculated value can then be expected.
The minimum advisable delay time can thus be calculated to be:
t_d = 2.1⋅ 10⁴ ⋅ 100 pF = 2.1 µs
The input C_t may be left open (unconnected) if no time delay, or only a very short one, is desired. In this case it is
however not possible to predict the value t_d of the time delay, since the parasitic capacitance at Pin 3 is influenced
by various factors, such as the sockets used, the metallisation on the circuit board, and the way it is constructed.
Figure 8. shows the dependence of the delay time t_d on the capacitance C_t.
1000 s
100 s
10 s
1s
100 ms
10 ms
1 ms
100 µs
10 µs
1 µs
100 ns
10 pF 100 pF 1 nF 10 nF 100 nF 1 µF 10 µF
100 µF 1000 µF 10 mF
Capacitance C_t
Figure 8. Dependence of the delay time on the capacitance C_t
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