THS7530 Datasheet, PDF (12/19 Pages) Texas Instruments – HIGH-SPEED, FULLY DIFFERENTIAL, CONTINUOUSLY VARIABLE GAIN AMPLIFIER

THS7530
SLOS405A DECEMBER 2002– REVISED APRIL 2003
1 kΩ
24.9 Ω
VIN+
VIN_–
1 kΩ
0.1 µF
24.9 Ω
VOCM
PD
0.1 µF
VCL+
VCL_–
0.1 µF
33 pF
24.9 Ω
THS7530
VG_–
VS_– ^VG+
24.9 Ω
33 pF
VS+ = 5 V
6.8 µF
VOUT+
VOUT_–
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Figure 24. DC-Coupled Differential Input With DC-Coupled Differential Output
LAYOUT CONSIDERATIONS
The THS7530 comes in a thermally enhance PowerPADt package. Figure 25 shows the recommended number of
vias and thermal land size recommended for best performance. Thermal vias connect the thermal land to internal
or external copper planes and should have a drill diameter sufficiently small so that the via hole is effectively plugged
when the barrel of the via is plated with copper. This plug is needed to prevent wicking the solder away from the
interface between the package body and the thermal land on the surface of the board during solder reflow. The
experiments conducted jointly with Solectron Texas indicate that a via drill diameter of 0.33mm (13 mils) or smaller
works well when 1 ounce copper is plated at the surface of the board and simultaneously plating the barrel of the via.
If the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used
to cap the vias with a dimension equal to the via diameter + 0,1 mm minimum. This prevents the solder from being
wicked through the thermal via and potentially creating a solder void in the region between the package bottom and
the thermal land on the surface of the PCB.
TSSOP
14 Pin PWP
2X3
3.4
5
Figure 25. Recommended Thermal Land Size and Thermal Via Patterns (dimensions in mm)
See TI’s Technical Brief titled PowerPADt Thermally Enhanced Package (SLMA002) for a detailed discussion of
the PowerPADt package, its dimensions, and recommended use.
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