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| JM38510-12501BGA Datasheet, PDF (12/21 Pages) Texas Instruments – LF198JAN Monolithic Sample-and-Hold Circuits | |||
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LF198JAN
SNOSAJ2A â FEBRUARY 2005 â REVISED MARCH 2013
www.ti.com
DIGITAL FEEDTHROUGH
Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the
amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as
possible from the analog input and the Ch pin. Grounded guarding traces may also be used around the input line,
especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also
help.
Guarding Technique
Figure 19. Use 10-pin layout. Guard around Chis tied to output.
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