BQ24610_2 Datasheet, PDF (12/33 Pages) Texas Instruments – Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger with System Power Selector and Low Iq

bq24610
bq24617
SLUS892 – DECEMBER 2009
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PIN
NO. NAME
1 ACN
2 ACP
3 ACDRV
4 CE
5 STAT1
6 TS
7 TTC
8 PG
9 STAT2
10 VREF
11 ISET1
12 VFB
13 SRN
14 SRP
15 ISET2
16 ACSET
17 GND
18 REGN
19 LODRV
20 PH
21 HIDRV
22 BTST
23 BATDRV
24 VCC
PowerPAD
Pin Functions – 24-Pin QFN
FUNCTION DESCRIPTION
Adapter current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. An optional 0.1-μF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.
Adapter current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. A 0.1-μF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.
AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET
and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and
slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to
source of the ACFET is used to slow down the ON and OFF times.
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor.
Open-drain charge status pin to indicate various charger operation (See Table 3)
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND. (See Figure 18)
SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer
and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed.
Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH
when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor.
Open-drain charge status pin to indicate various charger operation (See Table 3)
3.3V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for
programming of voltage and current regulation and for programming the TS threshold.
Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point.
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to
adjust the output battery regulation voltage.
Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
Pre-charge and termination current set input. The voltage of ISET2 pin programs the pre-charge current regulation set-point and
termination current trigger point.
Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power
Management (DPM)
Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.
PWM low side driver positive 6V supply output. Connect a 1-μF ceramic capacitor from REGN to GND pin, close to the IC. Use for
low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.
PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PH to BTST.
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from SW to BTST.
Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from
the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.
Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the
system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical
to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an
optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.
IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC.
Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND
and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
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