TMS320C6670 Datasheet, PDF (118/206 Pages) Texas Instruments – Multicore Fixed and Floating-Point System-on-Chip

TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
Table 7-15 TMS320C6670 System Event Mapping — C66x CorePac Primary Interrupts (Part 4 of 4)
Event Number
93
94
95
Interrupt Event
INTC0_OUT(13+16*n)⁷
INTC0_OUT(14+16*n)⁷
INTC0_OUT(15+16*n)⁷
Description
Interrupt Controller Output
Interrupt Controller Output
Interrupt Controller Output
96
INTERR
Dropped CPU interrupt event
97
EMC_IDMAERR
Invalid IDMA parameters
98
Reserved
99
Reserved
100
EFIINTA
EFI Interrupt from Side A
101
EFIINTB
EFI Interrupt from Side B
102
AIF_SEVT0
AIF System Event
103
AIF_SEVT0
AIF System Event
104
AIF_SEVT0
AIF System Event
105
AIF_SEVT0
AIF System Event
106
AIF_SEVT0
AIF System Event
107
AIF_SEVT0
AIF System Event
108
AIF_SEVT0
AIF System Event
109
AIF_SEVT0
AIF System Event
110
MDMAERREVT
VbusM error event
111
Reserved
112
TPCC0_EDMACC_AETEVT TPCC0 AET Event
113
PMC_ED
Single bit error detected during DMA read
114
TPCC1_EDMACC_AETEVT TPCC1 AET Event
115
TPCC2_EDMACC_AETEVT TPCC2 AET Event
116
UMC_ED1
Corrected bit error detected
117
UMC_ED2
Uncorrected bit error detected
118
PDC_INT
Power Down sleep interrupt
119
SYS_CMPA
SYS CPU MP fault event
120
PMC_CMPA
CPU memory protection fault
121
PMC_DMPA
DMA memory protection fault
122
DMC_CMPA
CPU memory protection fault
123
DMC_DMPA
DMA memory protection fault
124
UMC_CMPA
CPU memory protection fault
125
UMC_DMPA
DMA memory protection fault
126
EMC_CMPA
CPU memory protection fault
127
EMC_BUSERR
End of Table 7-15
Bus Error Interrupt
1. Core [n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn and TETBUNFLINTn.
2. Core [n] will receive SEMINTn and SEMERRn.
3. Core [n] will receive PCIEXpress_MSI_INTn and PCIEXpress_MSI_INTn+1.
4. Core [n] will receive MSMC_mpf_errorn.
5. Core [n] will receive GPINTn.
6. Core [n] will receive TINTLn and TINTHn.
7. For Core 0~3, it is INTC(interrupt number+17*n).
9. n is core number.
10. Core [n] will receive INTDST(n+16) and INTDST(n+20).
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118 TMS320C6670 Peripheral Information and Electrical Specifications
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