TMS320C6670 Datasheet, PDF (11/206 Pages) Texas Instruments – Multicore Fixed and Floating-Point System-on-Chip

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1 TMS320C6670 Features
TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689—November 2010
• Four TMS320C66x™ DSP Core Subsystems, Each With
– 1.2 GHz C66x Fixed/Floating-Point DSP Core
› 32 GMacs/Core for Fixed Point @ 1.2 GHz
› 16 GFlops/Core for Floating Point @ 1.2 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 2048 KB MSM SRAM Memory Shared by Four DSP
Cores
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Hardware Coprocessors
– Two Enhanced Coprocessors for Turbo Decoding
› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,
LTE, and WiMAX
› Supports up to 365 Mbps for LTE and up to
233 Mbps for WCDMA
› Low DSP Overhead – HW Interleaver Table
Generation and CRC Check
– One Enhanced Coprocessor for Turbo Encoding
› Supports up to 643 Mbps for LTE and up to 746
Mbps for WCDMA
– Four Viterbi Decoders
› Supports More Than 38 Mbps @ 40 bit Block Size
– Two Fast Fourier Transform Coprocessors
› 1365 pt FFT in 4.8 μs
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessors
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire Speed Throughput at 1.5M Packets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP and WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,
CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Four Rake/Search Accelerators (RSA) for
– Chip Rate Processing for WCDMA Rel'99, HSDPA,
and HSDPA+
– Reed-Muller Decoding
• Peripherals
– Six Lane SerDes-Based Antenna Interface (AIF2)
› Operating at up to 6.144 Gbps
› Compliant with OBSAI RP3 and CPRI Standards
for 3G / 4G (WCDMA, LTE TDD, LTE FDD,
TD-SCDMA, and WiMAX)
– Four Lanes of SRIO 2.1
› 5 GBaud Operation Per Lane
› Supports Direct I/O, Message Passing
– Two Lanes PCIe Gen2
› Supports Up To 5 GBaud
– Hyperlink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 50 Gbaud
– Ethernet MAC Subsystem (EMAC)
› Two SGMII Ports
› IEEE1588 Support
– 64-Bit DDR3 Interface
– UART Interface
– I²C Interface
– 16 GPIO pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 100°C
• Extended Temperature:
– - 40°C to 105°C
Copyright 2010 Texas Instruments Incorporated