TMS320C6416TBGLZA8 Datasheet, PDF (116/148 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009
PERIPHERAL COMPONENT INTERCONNECT (PCI) TIMING [C6415T AND C6416T ONLY]
(CONTINUED)
timing requirements for serial EEPROM interface (see Figure 50)
NO.
8 tsu(DIV-CLKH)
9 th(CLKH-DIV)
Setup time, XSP_DI valid before XSP_CLK high
Hold time, XSP_DI valid after XSP_CLK high
−600
−720
−850
−1G
MIN MAX
50
0
UNIT
ns
ns
switching characteristics over recommended operating conditions for serial EEPROM interface^†
(see Figure 50)
NO.
PARAMETER
1 tw(CSL)
Pulse duration, XSP_CS low
2 td(CLKL-CSL)
Delay time, XSP_CLK low to XSP_CS low
3 td(CSH-CLKH)
Delay time, XSP_CS high to XSP_CLK high
4 tw(CLKH)
Pulse duration, XSP_CLK high
5 tw(CLKL)
Pulse duration, XSP_CLK low
6 tosu(DOV-CLKH) Output setup time, XSP_DO valid before XSP_CLK high
7 toh(CLKH-DOV)
Output hold time, XSP_DO valid after XSP_CLK high
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.}
2
XSP_CS
3
4
5
XSP_CLK
XSP_DO
XSP_DI
6
7
9
8
−600
−720
−850
−1G
UNIT
MIN TYP MAX
4092P
ns
0
ns
2046P
ns
2046P
ns
2046P
ns
2046P
ns
2046P
ns
1
Figure 50. PCI Serial EEPROM Interface Timing
116
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443