TMS320C6416TBGLZA8 Datasheet, PDF (109/148 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

TMS320C6414T, TMS320C6415T, TMS320C6416T
FIXEDĆPOINT DIGITAL SIGNAL PROCESSORS
SPRS226M − NOVEMBER 2003 − REVISED APRIL 2009
HOST-PORT INTERFACE (HPI) TIMING
timing requirements for host-port interface cycles^†‡ (see Figure 39 through Figure 46)
NO.
1 tsu(SELV-HSTBL)
2 th(HSTBL-SELV)
3 tw(HSTBL)
4 tw(HSTBH)
10 tsu(SELV-HASL)
11 th(HASL-SELV)
12 tsu(HDV-HSTBH)
13 th(HSTBH-HDV)
14 th(HRDYL-HSTBL)
Setup time, select signals§ valid before HSTROBE low
Hold time, select signals§ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals§ valid before HAS low
Hold time, select signals§ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
−600
−850
−720
−1G
MIN MAX
5
2.4
4P¶
4P
5
2
5
2.8
2
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low
2
19 th(HSTBL-HASL)
Hold time, HAS low after HSTROBE low
2.1
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.}
§ _{Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.}
¶ _{Select the parameter value of 4P or 12.5 ns, whichever is greater.}
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating conditions during host-port interface
cycles^†‡ (see Figure 39 through Figure 46)
NO.
PARAMETER
−600
−850
−720
−1G
UNIT
6 td(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high#
MIN
MAX
1.3 4P + 8
ns
7 td(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an HPI read
2
ns
8 td(HDV-HRDYL)
9 toh(HSTBH-HDV)
15 td(HSTBH-HDHZ)
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
−3
ns
1.5
ns
12
ns
16 td(HSTBL-HDV)
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
4P + 8
ns
† _{HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.}
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.}
# _{This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)}
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
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