TMS320TCI6487 Datasheet, PDF (111/206 Pages) Texas Instruments – Communications Infrastructure Digital Signal Processor

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TMS320TCI6487
TMS320TCI6488
Communications Infrastructure Digital Signal Processor
SPRS358F – APRIL 2007 – REVISED AUGUST 2008
8.6.6 Reset Controller Register
The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This
register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see
Section 8.6.6.2).
8.6.6.1 Reset Type Status Register Description
The reset type status (RSTYPE) register latches the cause of the last reset. If multiple reset sources occur
simultaneously, this register latches the highest priority reset source. The reset type status register is
shown in Figure 8-6 and described in Section 8.6.6.2.
31
16
Reserved
R-0
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
4
3
2
1
0
SRST Rsvd WRST POR
R-0 R-0 R-0 R-0
Figure 8-6. Reset Type Status Register (RSTYPE) [Hex Address: 029A 00E4]
Table 8.6.6.2. Reset Type Status Register (RSTYPE) Field Descriptions
BIT
FIELD
31:4 Reserved
3 SRST
1 WRST
2 Reserved
0 POR
VALUE
DESCRIPTION
Reserved. The reserved bit location is always read as 0. A value written to this field has not effect.
System Reset.
0 System Reset was not the last reset to occur.
1 System Reset was the last reset to occur.
Warm Reset.
0 Warm Reset was not the last reset to occur.
1 Warm Reset was the last reset to occur.
Reserved. The reserved bit location is always read as 0. A value written to this field has not effect.
Power-on Reset.
0 Power-on Reset was not the last reset to occur.
1 Power-on Reset was the last reset to occur.
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Peripheral Information and Electrical Specifications 111