LMH1251MT-NOPB Datasheet, PDF (11/19 Pages) Texas Instruments – YPBPR Path: 70 MHz, −3 dB, 700 mVPP Bandwidth

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LMH1251
SNLS193J – AUGUST 2005 – REVISED MARCH 2013
1 H SYNC_IN
2 V SYNC_IN
3 R_IN
4 G_IN
5 B_IN
6 GND
7 V_CC
8 P_{R IN}
9 P_{B IN}
10 Y
11 SYNC on Y
12 GND
INPUT SELECT 24
AUTO/MANUAL ₂₃
DETECT SELECT
SD/HD SELECT* ²²
POWER SAVE 21
100 PF
R_OUT 20
100 PF ^{10 k:}
G_OUT 19
100 PF
B_OUT 18
V_CC 17
10 k:
LMH6734
33:
75:
33:
75:
33:
75:
10 k:
ROUT
G_OUT
B_OUT
GND 16
R_EXT 15
H SYNC_OUT 14
V SYNC_OUT 13
100:
100:
POSITIVE EDGE SYNCs
500:
500:
H SYNC_OUT
V SYNC_OUT
NEGATIVE
EDGE
SYNCs
Figure 8. Simplified Application Diagram for Driving a VGA Cable
LAYOUT CONSIDERATIONS
The most important point to note regarding the layout of the LMH1251 on a PCB is that the trace length between
the output pins of the LMH1251 and the input AC coupling capacitors of the next stage ADC or preamplifier must
be as minimal as possible. The trace lengths of the H Sync and V Sync outputs should also be minimized, as the
capacitive loading on these outputs must not exceed 6 pF. For long signal paths leading up to the input of the
LMH1251, controlled impedance lines should be used, along with impedance matching elements. Bypass
capacitors should be placed as close as possible to the supply pins of the device. The larger electrolytic bypass
capacitor can be located farther from the device. The 10 kΩ external resistor should also be placed as close as
possible to the R_EXT pin. All video signals must be kept away from the R_EXT pin (15). This pin has a very high
input impedance and will pick up any high frequency signals routed near it.
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