DAC3282_15 Datasheet, PDF (11/65 Pages) Texas Instruments – DAC3282 16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)

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DAC3282
SLAS646C – DECEMBER 2009 – REVISED MAY 2015
6.8 Timing Characteristics
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
ANALOG OUTPUT ⁽¹⁾
TEST CONDITIONS
MIN
TYP
MAX UNIT
t_s(DAC)
t_pd
Output settling time to 0.1%
Output propagation delay
Transition: Code 0x0000 to 0xFFFF
DAC outputs are updated on the
falling edge of DAC clock. Does not
include Digital Latency (see below).
10.4
ns
2
ns
t_r(IOUT)
t_f(IOUT)
Output rise time 10% to 90%
Output fall time 90% to 10%
DAC Wake-up Time
Power-up
time
DAC Sleep Time
IOUT current settling to 1% of
IOUT_FS. Measured from SDENB
rising edge; Register CONFIG24,
toggle sleepa from 1 to 0
IOUT current settling to less than
1% of IOUT_FS. Measured from
SDENB rising edge; Register
CONFIG24, toggle sleepa from 0 to
1.
220
ps
220
PS
90
μs
90
μs
TIMING LVDS INPUTS: DATACLKP/N, double edge latching – See Figure 25
t_s(DATA)
Setup time, D[7:0]P/N and
FRAMEP/N, valid to either edge of
DATACLKP/N
FRAMEP/N latched on rising edge
of DATACLKP/N only
0
ps
t_h(DATA)
Hold time, D[7:0]P/N and
FRAMEP/N, valid after either edge
of DATACLKP/N
FRAMEP/N latched on rising edge
of DATACLKP/N only
400
ps
t_(FRAME)
t_{_align}
FRAMEP/N pulse width
Maximum offset between
DATACLKP/N and DACCLKP/N
rising edges
f_DATACLK is DATACLK frequency in
MHz
FIFO Bypass Mode only
f_DACCLK is DACCLK frequency in
MHz
1/2f_DATACL
K
ns
1/2f_DACCLK
–0.55
ns
TIMING OSTRP/N Input: DACCLKP/N rising edge latching
t_s(OSTR)
Setup time, OSTRP/N valid to rising
edge of DACCLKP/N
200
ps
t_h(OSTR)
Hold time, OSTRP/N valid after
rising edge of DACCLKP/N
200
ps
SERIAL PORT TIMING – See Figure 40 and Figure 41
t_s(SDENB)
Setup time, SDENB to rising edge of
SCLK
20
ns
t_s(SDIO)
Setup time, SDIO valid to rising
edge of SCLK
10
ns
t_h(SDIO)
Hold time, SDIO valid to rising edge
of SCLK
5
ns
t_(SCLK)
Period of SCLK
Register CONFIG5 read
(temperature sensor read)
1
μs
All other registers
100
ns
t_(SCLKH)
High time of SCLK
Register CONFIG5 read
(temperature sensor read)
0.4
μs
All other registers
40
ns
t_(SCLKL)
Low time of SCLK
Register CONFIG5 read
(temperature sensor read)
0.4
μs
All other registers
40
ns
t_d(Data)
Data output delay after falling edge
of SCLK
10
ns
t_RESET
Minimum RESETB pulsewidth
25
ns
(1) Measured single ended into 50 Ω load.
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