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TLK1201ARCP Datasheet, PDF (10/21 Pages) Texas Instruments – ETHERNET TRANSCEIVERS
TLK1201ARCP, TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580A – FEBRUARY 2004 – REVISED JUNE 2004
DISSIPATION RATING TABLE
PACKAGE
RCP64 (2)
RCP64 (3)
RCP64 (4)
TA≤ 25°C
POWER RATING
5.25 W
3.17 W
2.01 W
OPERATING FACTOR(1)
ABOVE TA = 25°C
46.58 mW/°C
23.70 mW/°C
13.19 mW/°C
(1) This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA).
(2) 2 oz. Trace and copper pad with solder
(3) 2 oz. Trace and copper pad without solder
(4) Standard JEDEC high-K board
PARAMETER
RΘJA
Junction-to-free-air thermal re-
sistance
RΘJC
Junction-to-case-thermal resist-
ance
Thermal Characteristics
TEST CONDITION
Board-mounted, no air flow, high conductivity TI rec-
ommended test board, chip soldered or greased to thermal
land
Board-mounted, no air flow, high conductivity TI rec-
ommended test board with thermal land but no solder or
grease thermal connection to thermal land
Board-mounted, no air flow, JEDEC test board
Board-mounted, no air flow, high conductivity TI rec-
ommended test board, chip soldered or greased to thermal
land
Board-mounted, no air flow, high conductivity TI rec-
ommended test board with thermal land but no solder or
grease thermal connection to thermal land
Board-mounted, no air flow, JEDEC test board
www.ti.com
TA = 70°C
POWER RATING
2.89 W
1.74 W
1.11 W
MIN TYP MAX UNIT
21.47
°C/W
42.2
75.83
0.38
°C/W
0.38
7.8
RECOMMENDED OPERATING CONDITIONS
MIN
Supply voltage, VDD, VDD(A)
2.3
Total supply current, IDD, IDD(A)
Frequency = 1.25 Gbps, PRBS pattern
Total power dissipation, PD
Frequency = 1.25 Gbps, PRBS pattern
Frequency = 1.25 Gbps, worst case(1)
Total shutdown current, IDD, IDD(A)
Enable = 0, VDD(A), VDD = 2.7 V
Startup lock time, PLL
VDD, VDD(A) = 2.5 V, EN↑ to PLL acquire
TLK1201A
0
Operating free-air temperature, TA
TLK1201AI
-40
(1) The worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.
NOM
2.5
250
MAX
2.7
90
245
50
500
70
85
UNIT
V
mA
mW
mW
µA
µs
°C
REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
Frequency
Frequency
Accuracy
Duty cycle
Jitter
TEST CONDITIONS
Minimum data rate
TLK1201A
TLK1201AI
Maximum data rate
Random plus deterministic
MIN
TYP–0.01%
TYP–0.01%
TYP–0.01%
100
40%
TYP
60
60
130
50%
MAX
TYP+0.01%
TYP+0.01%
TYP+0.01%
100
60%
40
UNIT
MHz
ppm
ps
10