LP38502-ADJ Datasheet, PDF (10/27 Pages) Texas Instruments – LP3850x-ADJ, LP3850xA-ADJ 1.5-A Flexcap Low-Dropout Linear Regulatorfor 2.7-V to 5.5-V Inputs

LP38500-ADJ, LP38502-ADJ
SNVS539G – NOVEMBER 2007 – REVISED JUNE 2015
Functional Block Diagrams (continued)
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Figure 13. LP38502-ADJ WSON Block Diagram
7.3 Feature Description
7.3.1 Stability And Phase Margin
Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate
phase margin, which is defined as the difference between the phase shift and –180 degrees at the frequency
where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to
create a zero to add enough phase lead to ensure stable operation. The LP38500-ADJ and LP38502-ADJ each
have a unique internal compensation circuit which maintains phase margin regardless of the ESR of the output
capacitor, so any type of capacitor may be used.
Figure 14 shows the gain/phase plot of the LP38500-ADJ and LP38502-ADJ with an output of 1.2 V, a 10-µF
ceramic output capacitor, delivering 1.5 A of load current. It can be seen that the unity-gain crossover occurs at
150 kHz, and the phase margin is about 40° (which is very stable).
Figure 14. Gain-Bandwidth Plot for 1.5-A Load
Figure 15 shows the gain and phase with no external load. In this case, the only load is provided by the gain
setting resistors (about 12 kΩ total in this test). It is immediately obvious that the unity-gain frequency is
significantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.
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