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LP38500-ADJ Datasheet, PDF (10/23 Pages) National Semiconductor (TI) – 1.5A FlexCap Low Dropout Linear Regulator for 2.7V to 5.5V Inputs
LP38500-ADJ, LP38502-ADJ
SNVS539F – NOVEMBER 2007 – REVISED APRIL 2013
www.ti.com
STABILITY AND PHASE MARGIN
Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate
phase margin, which is defined as the difference between the phase shift and -180 degrees at the frequency
where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to
create a zero to add enough phase lead to ensure stable operation. The LP38500/2-ADJ has a unique internal
compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, so any type of
capacitor may be used.
Figure 23 shows the gain/phase plot of the LP38500/2-ADJ with an output of 1.2V, 10 µF ceramic output
capacitor, delivering 1.5A of load current. It can be seen that the unity-gain crossover occurs at 150 kHz, and the
phase margin is about 40° (which is very stable).
Figure 23. Gain-Bandwidth Plot for 1.5A Load
Figure 24 shows the gain and phase with no external load. In this case, the only load is provided by the gain
setting resistors (about 12 kΩ total in this test). It is immediately obvious that the unity-gain frequency is
significantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.
Figure 24. Gain-Bandwidth Plot for No Load
The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FET
or PNP pass transistor, because they have a pole in the loop gain function given by:
(2)
This illustrates how the pole goes to the highest frequency when RL is minimum value (maximum load current).
In general, LDO’s have maximum bandwidth (and lowest phase margin) at full load current. In the case of the
LP38500/2-ADJ, it can be seen that it has good phase margin even when using ceramic capacitors with ESR
values of only a few milli Ohms.
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