LP2995LQ Datasheet, PDF (10/22 Pages) Texas Instruments – LP2995 DDR Termination Regulator

LP2995
SNVS190M – FEBRUARY 2002 – REVISED MARCH 2013
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100
90
80
70
60
50
40
0
1
2
3
4
NUMBER OF VIAS
Figure 15. WQFN-16 θ_JA vs # of Vias (4 Layer JEDEC Board))
Additional improvements in lowering the θ_JA can also be achieved with a constant airflow across the package.
Maintaining the same conditions as above and utilizing the 2x2 via array, Figure 16 shows how the θ_JA varies
with airflow.
51
50
49
48
47
46
45
0
100 200 300 400 500 600
AIRFLOW (Linear Feet Per Minute)
Figure 16. θ_JA vs Airflow Speed (JEDEC Board with 4 Vias)
Typical Application Circuits
The typical application circuit used for SSTL-2 termination schemes with DDR-SDRAM can be seen in Figure 17.
VDDQ
LP2995
VDDQ
VREF
VREF
VDD
+
CIN
AVIN
VTT
PVIN
VSENSE
GND
VTT
+
COUT
Figure 17. SSTL-2 Implementation
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