TLC876M Datasheet, PDF (1/23 Pages) Texas Instruments – 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTERS

D 10-Bit Resolution 20 MSPS Sampling
Analog-to-Digital Converter (ADC)
D Power Dissipation . . . 107 mW Typ
D 5-V Single Supply Operation
D Differential Nonlinearity . . . ±0.5 LSB Typ
D No Missing Codes
D Power Down (Standby) Mode
D Three State Outputs
D Digital I/Os Compatible With 5-V or 3.3-V
Logic
D Adjustable Reference Input
D Small Outline Package (SOIC), Super Small
Outline Package (SSOP), or Thin Small
Outline Package (TSOP)
D Pin Compatible With the Analog
Devices AD876
TLC876M, TLC876I, TLC876C
10-BIT 20 MSPS PARALLEL OUTPUT CMOS
ANALOG-TO-DIGITAL CONVERTERS
SLAS140D – JULY 1997 – REVISED MAY 2000
DB, DW, OR PW PACKAGE
(TOP VIEW)
AGND ₁
DRV_{DD 2}
D0 ₃
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
D8 11
D9 12
DRGND 13
DGND 14
28 ^AV_DD
27 ^AIN
26 ^CML
25 REFBS
24 REFBF
23 NC
22 REFTF
21 REFTS
20 DGND
19 AGND
18 DV_DD
17 STBY
16 OE
15 CLK
applications
D Communications
D Multimedia
D Digital Video Systems
D High-Speed DSP Front-End . . . TMS320C6x
NC – No internal connection
description
The TLC876 is a CMOS, low-power, 10-bit, 20 MSPS analog-to-digital converter (ADC). The speed, resolution,
and single-supply operation are suited for applications in video, multimedia, imaging, high-speed acquisition,
and communications. The low-power and single-supply operation satisfy requirements for high-speed portable
applications. The speed and resolution ideally suit charge-coupled device (CCD) input systems such as color
scanners, digital copiers, electronic still cameras, and camcorders. A multistage pipelined architecture with
output error correction logic provides for no missing codes over the full operating temperature range. Force and
sense connections to the reference inputs provide a more accurate internal reference voltage to the reference
resistor string.
A standby mode of operation reduces the power to typically 15 mW. The digital I/O interfaces to either 5-V or
3.3-V logic and the digital output terminals can be placed in a high-impedance state. The format of the output
data is straight binary coding.
A pipelined multistaged architecture achieves a high sample rate with low power consumption. The TLC876
distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively
higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a
small fraction of the 1023 comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within
each of the stages permits the first stage to operate on a new input sample while the second through the fifth
stages operate on the four preceding samples.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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