CD54ACT112_08 Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT112, CD74ACT112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS323 – JANUARY 2003
D Inputs Are TTL-Voltage Compatible
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
CD54ACT112 . . . F PACKAGE
CD74ACT112 . . . M PACKAGE
(TOP VIEW)
1CLK 1
1K 2
1J 3
1PRE 4
1Q 5
1Q 6
2Q 7
GND 8
16 V_CC
15 1CLR
14 2CLR
13 2CLK
12 2K
11 2J
10 2PRE
9 2Q
description/ordering information
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC – M
–55°C to 125°C
Tube
CD74ACT112M
Tape and reel CD74ACT112M96
ACT112M
CDIP – F
Tube
CD54ACT112F3A
CD54ACT112F3A
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUTS
PRE CLR CLK J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H‡ H‡
H
H
↓
L
L
Q0 Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
Toggle
H
H
H
X
X
Q0 Q0
‡ _{Output states are unpredictable if PRE and CLR go high}
simultaneously after both being low at the same time.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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