74HC194N Datasheet, PDF (1/19 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

Data sheet acquired from Harris Semiconductor
SCHS164G
September 1997 - Revised May 2006
CD54HC194, CD74HC194,
CD74HCT194
High-Speed CMOS Logic
4-Bit Bidirectional Universal Shift Register
[ /Title
(CD74
HC194,
CD74H
CT194)
/Sub-
ject
(High-
Speed
CMOS
Logic
4-Bit
Features
Description
• Four Operating Modes
- Shift Right, Shift Left, Hold and Reset
• Synchronous Parallel or Serial Operation
• _TTAyp=ic2a5l_ofC_MAX = 60MHz at V_CC = 5V, C_L = 15pF,
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
The ’HC194 and CD74HCT194 are 4-bit shift registers with
Asynchronous Master Reset (MR). In the parallel mode (S0
and S1 are high), data is loaded into the associated flip-flop
and appears at the output after the positive transition of the
clock input (CP). During parallel loading serial data flow is
inhibited. Shift left and shift right are accomplished
synchronously on the positive clock edge with serial data
entered at the shift left (DSL) serial input for the shift left
mode, and at the shift right (DSR) serial input for the shift
right mode. Clearing the register is accomplished by a Low
applied to the Master Reset (MR) pin.
Ordering Information
PART NUMBER
CD54HC194F3A
CD74HC194E
CD74HC194M
CD74HC194MT
CD74HC194M96
CD74HC194NSR
CD74HC194PW
CD74HC194PWR
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
Pinout
CD54HC194 (CERDIP)
CD74HC194 (PDIP, SOIC, SOP, TSSOP)
CD74HCT194 (PDIP)
TOP VIEW
CD74HC194PWT
-55 to 125
16 Ld TSSOP
CD74HCT194E
-55 to 125
16 Ld PDIP
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
MR 1
DSR 2
D₀ 3
D₁ 4
D₂ 5
D₃ 6
DSL 7
GND 8
16 V_CC
15 Q₀
14 Q₁
13 Q₂
12 Q₃
11 CP
10 S1
9 S0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2006, Texas Instruments Incorporated
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