THC63LVD104S Datasheet, PDF (3/12 Pages) THine Electronics, Inc. – 112MHz 30Bits Color LVDS Receiver

THC63LVD104S Rev.1.0
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RE+,RE-
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
Pin No.
50, 49
52, 51
55, 54
60, 59
62, 61
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
PD
3
OE
4
DK
2
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
5
9,23,37,48
31
1,16,30,44
53
58
64
63
I/O Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
( 3-Level )
IN
Power
OUT
Ground
Power
Ground
Power
Ground
Description
LVDS Data In.
LVDS Clock In.
CMOS/TTL Data Outputs.
Power down and Output Control.(Table1)
H: Normal operation
L: Power down
Output Enable. See Table1.
H:Output enable.
L:Output disable
Output Clock Delay Timing Select.(Fig5)
t_RCP=Output Clock Cycle
L: Offset 0[nsec]
M: Offset
-
3
-t-R-----C----P--
14
(typ) [nsec]
H: Offset + 3-t-R-----C----P-- (typ)[nsec]
14
Output Clock Triggering Edge Select.(Fig5)
H: Rising Edge
L: Falling Edge
Power Supply Pins for TTL outputs and digital
circuitry.
Clock out.
Ground Pins for TTL outputs and digital circuitry.
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Copyright 2004 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.