SI8416DB Datasheet, PDF (7/8 Pages) Vishay Siliconix – N-Channel 8 V (D-S) MOSFET

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Package Information
Vishay Siliconix
MICRO FOOT^®: 6-Bump
(1.5 mm x 1 mm, 0.5 mm Pitch, 0.250 mm Bump Height)
XXXX
XXX
Mark on Backside of Die
6x Ø 0.24 to 0.26 (Note 3)
Solder mask ~ Ø 0.25
A
B
C
6x Ø b1
D
S
S
D
S
G
s
e
e
s
E
b
NOTE 5
e
e
K
Bump (Note 2)
Recommended Land Pattern
Notes
(unless otherwise specified)
1. Six (6) solder bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
DIM.
A
A₁
A₂
b
b1
e
s
D
E
K
MIN.
0.510
0.220
0.290
0.297
0.210
0.920
1.420
0.028
MILLIMETERS
NOM.
0.575
0.250
0.300
0.330
0.250
0.500
0.230
0.960
1.460
0.065
Note
• Use millimeters as the primary measurement.
MAX.
0.590
0.280
0.310
0.363
0.250
1.000
1.500
0.102
MIN.
0.0201
0.0087
0.0114
0.0116
0.0082
0.0362
0.0559
0.0011
INCHES
NOM.
0.0226
0.0098
0.0118
0.0129
0.0098
0.0197
0.0090
0.0378
0.0575
0.0025
MAX.
0.0232
0.0110
0.0122
0.0143
0.0098
0.0394
0.0591
0.0040
ECN: T15-0140-Rev. A, 20-Apr-15
DWG: 6035
Revison: 20-Apr-15
1
Document Number: 69426
For technical questions, contact: [e-mail]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000