71M6521DE Datasheet, PDF (40/101 Pages) Teridian Semiconductor Corporation – Energy Meter IC

71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
PB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
62 57 3 - 37 38 39 40 41 42 43 44 -- -- 20 21
65 60 3 5 39 40 41 42 43 44 45 46 -- -- 21 22
0 1 2 3 4 5 6 7 0 1 2 3 -- -- 6 7
DIO0=P0 (SFR 0x80)
DIO1=P1 (SFR 0x90)
0 1 2 3 4 5 6 7 0 1 2 3 -- -- 6 7
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Y Y Y Y Y Y Y Y Y Y Y Y -- -- -- --
DIO
Pin no. (64 LQFP)
Pin no. (68 QFN)
Data Register
Direction Register
Internal Resources
Configurable
16 17 18 19 20 21 22 23
22 12 -- -- -- -- -- --
23 13 -- 24 47 68
0 1 -- 3 4 5 -- --
DIO2=P2 (SFR 0xA0)
0 1 -- 3 4 5 -- --
DIO_DIR2 (SFR 0xA1)
N N -- N N N -- --
Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups
DIO_DIR [n]
DIO Pin n Function
0
Input
1
Output
Table 55: DIO_DIR Control Bit
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,
VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5
can be configured to implement the EEPROM Interface.
The PB pin is a dedicated digital input. If the optical UART is not used, OPT_TX and OPT_RX can be configured as dedicated
DIO pins (DIO1, DIO2, see Optical Interface section).
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, to individually assign an internal resource such as an interrupt or a timer control (see Table 54 for DIO pins
available for this option). This way, DIO pins can be tracked even if they are configured as outputs.
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in Figure 8,
right), not source it from V3P3D (as shown in Figure 8, left). This is due to the resistance of the internal
switch that connects V3P3D to either V3P3SYS or VBAT.
When configured as inputs, the dual-function (DIO/SEG) pins should not be pulled above V3P3SYS in
MISSION and above VBAT in LCD and BROWNOUT modes. Doing so will distort the LCD waveforms of the
other pins. This limitation applies to any pin that can be configured as a LCD driver.
The control resources selectable for the DIO pins are listed in Table 56. If more than one input is connected to the same
resource, the resources are combined using a logical OR.
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