U3741BM Datasheet, PDF (9/25 Pages) ATMEL Corporation – UHF ASK RECEIVER IC

U3741BM
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling
logic is enabled.
I_S = I_Soff
T_Sleep = Sleep × X_Sleep × 1024 × T_Clk
Start-up mode:
The signal processing circuits are
enabled. After the start-up time
(T_Startup) all circuits are in stable
condition and ready to receive.
I_S = I_Soff
T_Startup
Sleep:
X_Sleep:
T_Clk:
T_Startup:
5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
Extension factor defined by
XSleep_Std and XSleep_Temp
according to table 8
Basic clock cycle defined by f_XTO
and Pin MODE
Is defined by the selected baud rate
range and T_Clk. The baud rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
Bitcheck mode:
The incomming data stream is
analyzed. If the timing indicates a
valid transmitter signal, the receiver is
set to receiving mode. Otherwise it is
set to Sleep mode.
I_S = I_Soff
T_{Bitcheck Bitcheck}
NO
OK ?
YES
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected mC. It can be set to Sleep
mode through an OFF command via
Pin DATA or ENABLE.
I_S = I_{Soff OFF command}
T_Bitcheck:
Depends on the result of the
bitcheck
If the bitcheck is ok, T_Bitcheck
depends on the number of bits to be
checked (N_Bitcheck) and on the
utilized data rate.
If the bitcheck fails, the average
time period for that check depends
on the selected baud rate range and
on T_Clk. The baud rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
Figure 10. Polling mode flow chart
( Number of checked Bits: 3 )
Enable IC
Bitcheck ok
Bitcheck
Dem_out
DATA
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Polling – Mode
Receiving mode
Figure 11. Timing diagram for complete sucessful bitcheck
Rev. A1, 15-Oct-98
9 (25)
Preliminary Information