U3741BM Datasheet, PDF (11/25 Pages) ATMEL Corporation – UHF ASK RECEIVER IC

U3741BM
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck failed ( CV_Lim < Lim_min )
Bitcheck
Dem_out
1/2 Bit
Bitcheck–Counter
0
1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12
Startup – Mode
Bitcheck – Mode
0
Sleep–Mode
Figure 14. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_min)
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck failed ( CV_Lim = Lim_max )
Bitcheck
Dem_out
1/2 Bit
Bitcheck–Counter
0
1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Startup – Mode
Bitcheck – Mode
0
Sleep–Mode
Figure 15. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_max)
Duration of the Bitcheck
If no transmitter signal is present during the bitcheck, the
output of the ASK/ FSK demodulator delivers random
signals. The bitcheck is a statistical process and T_Bitcheck
varies for each check. Therefore, an average value for
T_Bitcheck is given in the electrical characteristics.
T_Bitcheck depends on the selected baudrate range and on
T_Clk. A higher baudrate range causes a lower value for
T_Bitcheck resulting in a lower current consumption for
polling mode.
In the presence of a valid transmitter signal, T_Bitcheck is
dependant on the frequency of that signal, f_Sig and the
count of the checked bits, N_Bitcheck. A higher value for
N_Bitcheck thereby results in a longer period for T_Bitcheck
requiring a higher value for the transmitter pre-burst
T_Preburst.
Receiving Mode
If the bitcheck is successful for all bits specified by
N_Bitcheck, the receiver switches to receiving mode.
According to figure 11, the internal data signal is
switched to Pin DATA in that case. A connected µC can
be woken up by the negative edge at Pin DATA. The
receiver stays in that condition until it is switched back to
polling mode explicitly.
Digital Signal Processing
The data from the ASK/ FSK demodulator (Dem_out) is
digitally processed in different ways and as a result
converted into the output signal data. This processing
depends on the selected baudrate range (BR_Range).
Figure 16 illustrates how Dem_out is synchronized by the
extended clock cycle T_XClk. This clock is also used for the
Bitcheck counter. Data can change its state only after
T_XClk elapsed. The edge-to-edge time period t_ee of the
Data signal as a result is always an integral multiple of
T_XClk.
The minimum time period between two edges of the data
signal is limited to t_ee ≥ T_{DATA_min}. This implies an
efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at
DATA. This eases the interrupt handling of a connected
µC. T_{DATA_min} is to some extent affected by the preceding
edge-to-edge time interval t_ee as illustrated in figure 17.
If t_ee is in between the specified bitcheck limits, the
following level is frozen for the time period
T_{DATA_min} = tmin1, in case of t_ee being outside that
bitcheck limits T_{DATA_min} = tmin2 is the relevant stable
time period.
The maximum time period for DATA to be Low is limited
to T_{DATA_L_max}. This function is employed to ensure a
finite response time in programming or switching off the
receiver via Pin DATA. T_{DATA_L_max} is thereby longer
than the maximum time period indicated by the
transmitter data stream. Figure 18 gives an example
where Dem_out remains Low after the receiver is in
receiving mode.
Rev. A1, 15-Oct-98
Preliminary Information
11 (25)