U3741BM Datasheet, PDF (7/25 Pages) ATMEL Corporation – UHF ASK RECEIVER IC

U3741BM
The U3741BM is designed to operate with data coding
where the DC level of the data signal is 50%. This is valid
for Manchester and Bi-phase coding. If other modulation
schemes are used, the DC level should always remain
within the range of V_{DC_min} = 33% and V_{DC_max} = 66%.
The sensitivity may be reduced by up to 1.5 dB in that
condition.
Each BR_Range is also defined by a minimum and a
maximum edge-to-edge time (t_{ee_sig}). These limits are
defined in the electrical characteristics. They should not
be exceeded to maintain full sensitivity of the receiver.
Receiving Characteristics
The RF receiver U3741BM can be operated with and
without a SAW front end filter. In a typical automotive
application, a SAW filter is used to achieve better
selectivity. The selectivity with and without a SAW front
end filter is illustrated in figure 8. This example relates to
ASK mode and the 300-kHz bandwidth version of the
U3741BM. FSK mode and the 600-kHz version of the
receiver exhibit similar behavior. Note that the mirror
frequency is reduced by 40 dB. The plots are printed rela-
tively to the maximum sensitivity. If a SAW filter is used,
an insertion loss of about 4 dB must be considered.
When designing the system in terms of receiving
bandwidth, the LO deviation must be considered as it also
determines the IF center frequency. The total LO
deviation is calculated to be the sum of the deviation of
the crystal and the XTO deviation of the U3741BM. Low-
cost crystals are specified to be within ±100 ppm. The
XTO deviation of the U3741BM is an additional devi-
ation due to the XTO circuit. This deviation is specified
to be ±30 ppm. If a crystal of ±100 ppm is used, the total
deviation is ±130 ppm in that case. Note that the receiving
bandwidth and the IF-filter bandwidth are equivalent in
ASK mode but not in FSK mode.
Polling Circuit and Control logic
The receiver is designed to consume less than 1 mA while
being sensitive to signals from a corresponding
transmitter. This is achieved via the polling circuit. This
circuit enables the signal path periodically for a short
time. During this time the bitcheck logic verifies the
presence of a valid transmitter signal. Only if a valid
signal is detected the receiver remains active and
transfers the data to the connected µC. If there is no valid
signal present the receiver is in sleep mode most of the
time resulting in low current consumption. This condition
is called polling mode. A connected µC is disabled during
that time.
All relevant parameters of the polling logic can be
configured by the connected µC. This flexibility enables
the user to meet the specifications in terms of current
consumption, system response time, data rate etc.
Regarding the number of connection wires to the mC, the
receiver is very flexible. It can be either operated by a
single bi-directional line to save ports to the connected
mC. Or it can be operated by up to three uni-directional
ports.
Basic Clock Cycle of the Digital Circuitry
The complete timing of the digital circuitry and the
analog filtering is derived from one clock. According to
figure 9, this clock cycle T_Clk is derived from the crystal
oscillator (XTO) in combination with a divider. The
division factor is controlled by the logical state at Pin
MODE. According to chapter ‘RF Front End’, the
frequency of the crystal oscillator (f_XTO) is defined by the
RF input signal (f_RFin) which also defines the operating
frequency of the local oscillator (f_LO).
0
–10
without SAW
–20
–30
–40
–50
–60
–70
–80
with SAW
–90
–100
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
df ( MHz )
Figure 8. Receiving frequency response
TClk
Divider
:14/:10
fXTO
XTO
MODE
L : USA(:10)
16
H: Europe(:14)
DVCC
15
XTO
14
Figure 9. Generation of the basic clock cycle
Rev. A1, 15-Oct-98
7 (25)
Preliminary Information