U2784B Datasheet, PDF (7/11 Pages) TEMIC Semiconductors – 2200 MHz / 200 MHz Twin PLL

Timing Diagram Serial Bus
Data
Clock
Enable
t_SEC t_CH t_CL
Internal
Loadpulse
U2784B
t_SDC
t_HDC
t_EL
t_HCE t_HEC
96 11828
Clock High Time
t_CH
> 750
ns
Clock Low Time
t_CL
> 350
ns
Clock Period
t_PER
> 1100
ns
Set up Time Data to Clock
t_SDC
> 100
ns
Hold Time Data to Clock
t_HDC
> 400
ns
Hold Time Clock to Enable
t_HCE
> 400
ns
Hold Time Enable to Clock
t_HEC
> 400
ns
Enable Low Time
t_EL
> 200
ns
Set up Time Enable to Clock
t_SEC
> 4000
ns
TELEFUNKEN Semiconductors
Rev. A2, 29-Jul-96
7 (11)